Silicon-carbide mosfet cell structure and method for forming same

ABSTRACT

In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well (P type) and two parallel sources (N type) formed within the well. A Number of source rungs (doped N) connect sources at multiple locations. Regions between two rungs comprise a body (P type). These features are formed on an N-type epitaxial layer, which is formed on an N-type substrate. A contact extends across and contacts a number of source rungs and bodies. Gate oxide and a gate contact overlie a leg of a first well and a leg of a second adjacent well, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a division of U.S. patent application Ser. No.13/190,723, Stephen Daley Arthur et al., entitled “A silicon-carbideMOSFET cell structure and method for forming same,” which patentapplication is incorporated by reference herein in its entirety.

FIELD OF INVENTION

Embodiments presented herein relate generally to a silicon-carbide (SiC)metal-oxide semiconductor field effect transistor (MOSFET) cellstructure and a method for forming the SiC MOSFET.

BACKGROUND OF INVENTION

In a conventional lateral MOSFET current flows horizontally from sourceto drain (both source and drain regions doped with a material of a firstconductivity type) along a narrow channel doped with a material of asecond conductivity type. A voltage applied to a gate contact overlyingthe channel inverts the conductivity of the channel, allowing majoritycarriers to flow from source to drain. Because the channel is narrow,conventional MOSFETS have small drain currents and correspondingly lowpower ratings.

Power (high current) MOSFETS use many different device geometries toincrease the device's maximum current and power rating. These deviceshave current ratings from about 1 A to 200 A and power ratings fromabout 1 W to more than 500 W. A typical power MOSFET is not a lateraldevice. Instead, current flows from a source region on a top surface ofthe device vertically to a drain region on a bottom surface. Thisvertical channel configuration allows packing more channels (and moreMOSFETS) in a smaller area than a lateral MOSFET. A single die can carrymore parallel vertical MOSFET elements than horizontal (lateral) MOSFETelements.

There are three types of so-called vertical MOSFETs: planardouble-diffused, trench-gated, and pillar-gated. Each configuration hasa unique configuration and fabrication methodology.

In the planar double-diffused type, carriers (electrons in an NMOSdevice) flow from a first doped region (the source) along a top surfaceof the device, through the channel in a body region, and then turndownwardly to a second doped region on the bottom surface (the drain).The gate is located on the top surface of the device overlying thechannel. The body/channel region is formed of an opposite-conductivitymaterial than the drain and source regions. These planar double-diffusedvertical MOSFETs have a higher current capacity than their lateralcounterparts.

In the trench-gated MOSFET, the gate is formed in a trench that extendsvertically or near-vertically downwardly from the top surface of thedevice. The channel regions are formed along sidewalls of the trench.The source and drain regions can be located on a top surface of thesemiconductor bulk or disposed on opposing surfaces of the bulk.Trench-gated devices are advantageous because they occupy less surfacearea than vertical double-diffused MOSFETs and consequently enjoy ahigher device density. Pillar-gated devices are the converse of thetrench-gated device.

Enhancing semiconductor device performance and increasing device density(more devices per unit area) have always been and will always beimportant objectives of the semiconductor industry. Device density isincreased by making individual devices smaller and packing devices morecompactly. Packing more devices into the same area, or even better intoa smaller area, allows higher levels of system integration and in thecase of power MOSFETS, increased current capacity. Since the channellength consumes considerable space in the conventional lateral MOSFET, avertical channel conserves considerable space.

As device dimensions (also referred to as the feature sizes or designrules, and typically referring to the gate mask dimension) decrease topack the devices more closely, methods for forming devices and theirconstituent elements must adapt to the smaller feature sizes. Butshrinking device dimensions encounters certain manufacturinglimitations, especially with respect to lithographic processes.Fabricators of such devices have therefore sometimes turned to the useof self-alignment techniques to form the various device features.

FIG. 1 illustrates a simple prior art vertical NMOSFET 10 with twosource contacts (ohmic contact) 14 on each side of a gate oxide 16. Agate contact 18 overlies the gate oxide 16. N+ source regions 20 areformed in a P-well 24A. An extension of the P-well 24A comprises a P+region 24B. The source contacts 14 short each of the N+ source regions20 to the proximate P+ region 24B. Hereinafter, dopants for dopingvarious MOSFET regions may be referred to as dopants of a first or asecond conductivity type, where dopants of a first conductivity type canbe n-type dopants or p-type dopants, and similarly dopants of the secondconductivity type can be n-type dopants or p-type dopants.

An N− epitaxial drift layer 26 is disposed as shown, and an N+ substrate28 is disposed below the N− epitaxial layer 26. A drain contact 30 isformed on the N+ substrate 28.

When a gate-source voltage is greater than a gate-source thresholdvoltage, (which is a characteristic of the device) channel regions 24Awithin the P-wells 24 are inverted. Free electrons then flow from thesource regions 20 through the inverted channel regions 24A andvertically downwardly to the drain 30 along paths indicated generally bya reference character 40. Because the conducting channel is much widerthan in a conventional lateral MOSFET, the current can be much larger,permitting the vertical MOSFET (VMOSFET) to function at the current andpower levels required of a power MOSFET. NMOSFETS are almost universallyused in high power MOSFET applications.

To increase the current capacity of a vertical power MOSFET, a geometricpattern of individual MOSFET cells (a cell comprising the verticalMOSFET 10 illustrated in FIG. 1, for example) is formed on a substrateand the MOSFETS connected in parallel. The individual cells may be inthe shape of a closed figure, such as a square or hexagon, or they maybe arranged in parallel longitudinal stripes. Generally, because oftheir operational characteristics and geometry, parallel-connected powerMOSFETS have equal drain currents. In fact, it is this feature thatpermits parallel connection of the MOSFETS.

FIGS. 2 and 3 illustrate a top view and a cross-sectional view,respectively, of a prior art geometric pattern of cells arranged in aseries of parallel longitudinal stripes. Only two adjacent MOSFETS 38and 39 are illustrated in FIG. 2. A boundary between the MOSFETS 38 and39 is defined by adjacent gate contact stripes 40L and 40R, whichtogether define a gate 40. A leftmost boundary of the cell 38 is definedby a gate stripe 44L and a rightmost boundary of the cell 39 is definedby a gate stripe 46R. However, the gate stripe 44L and the gate stripe44R comprise only one-half of their respective gates, as another gatestripe (not shown) is adjacent each of the gate stripes 44L and 44R.

Continuing with FIG. 2, an interior of the cell 38 comprises sourcestripes 52L and 54L and an intermediate body stripe 56L. An interior ofthe cell 39 comprises source stripes 58R and 60R and an intermediatebody stripe 62R. The source stripes 52L, 54L, 58R and 60R and the bodyregions 56L and 62R are connected to respective contacts notillustrated. As shown in FIG. 3, the body region 62R extends below thesource regions h58R and 60R and the body region 56L extends below thesource regions 52L and 54L.

Channels are formed in the body region 62R at regions 70R and 72R byaction of a voltage applied to the respective gate contacts 40R and 46R.Channels are formed in the body region 56L at locations 80L and 82L byapplying a voltage to the respective gates 40L and 44L. The body regionsand the source regions may be shorted to prevent a parasitic bipolartransistor (as formed at the junction) from turning on.

Continuing with FIG. 3, gate oxide layers 90L, 92L, 94R and 96R underliethe respective gate contacts 44L, 40L, 40R and 46R. An N-epitaxial layer90 and a substrate 94 underlie the various doped regions as illustrated.A drain contact 99 is disposed on a back or bottom surface as shown.

A voltage applied to the gate contacts 44L, 40L, 40R and 46R inverts thechannel regions 82L, 80L, 70R and 72R, permitting carriers to flow fromthe source regions 54L, 52L, 58R and 60R through the inverted channelregions to the drain contact 99.

The channel resistance is one of the largest components of the totalon-state resistance between the source and drain in a MOSFET, referredto as R_(DS(ON)). The other resistive components arise in a vertical orpower MOSFET due to: source contact resistance, resistance to lateralflow of electrons across the source, channel resistance, JFET resistancethrough a constricted channel along the surface current path between theP-well regions, resistance across the N− epitaxial region (the currentspreads out as it flows vertically), substrate resistance as the currentflow vertically across the N+ substrate, and finally drain contactresistance. The channel resistance component can be as much as about 40%of R_(DS(ON) for a) 1200 volt SiC device, which is in part due to thepoor mobility of the inversion layers in SiC. Thus short channels andhigh channel density may be desired.

The channel resistance is directly related to the mobility of thecarriers within the (inverted) channel. For a silicon MOSFET the carriermobility is about 200 cm²/V-s. For silicon carbide the mobility falls toabout 20 cm²/V-s. Thus silicon carbide material has a higher channelresistance. To overcome this disadvantage of silicon carbide, it isdesirable to make the channel very short and densely pack them toincrease the number of vertical channels per unit area. The verticalchannels within the device are connected in parallel and act likeparallel resistors, which therefore lowers the total channel resistanceof the power MOSFET. The more channels that can be squeezed into a unitarea the smaller the resistance of the parallel-connected MOSFETchannels.

Notwithstanding its greater channel resistance, silicon carbide offerscertain advantages over a silicon power MOSFET. These advantages are aconsequence of the inherent material characteristics of SiC over Si,including a wider bandgap (3.2 eV), a higher voltage breakdown strength(2.2 MV/cm) and a higher thermal conductivity (˜3 W/cm-K). Butprocessing issues associated with the use of SiC material, includingpoor SiC-oxide interfaces and premature breakdown of the gate oxide,have disfavored widespread use of this material for commercial devices.

Various fabrication processes and device structures have been used toprovide accurate and reliable regions of power MOSFET devices, some ofwhich have been described above. However, continued improvements areneeded, especially as feature dimensions shrink and alignment tolerancesbecome more difficult to satisfy. But self alignment techniques provideaccurate and repeatable device structures and therefore increases deviceyield. Therefore use of self alignment techniques while shrinkingfeature sizes allows the devices to be packed more tightly. Shrinkingcell dimensions reduces the channel length, lowering the ON statechannel resistance (R_(DS(ON))).

BRIEF DESCRIPTION

In one embodiment, a method comprising, forming a well within a firstmaterial layer, the well having a generally U-shape in an XYcross-sectional plane, the first material layer doped a firstconductivity type, the well doped a second conductivity type and anintermediate region between upright legs of the U-shaped well doped afirst conductivity type; forming first and second sources within theintermediate region, the first and second sources spaced apart in an Xdirection and doped the first conductivity type; forming body regionswithin the intermediate region, the body regions between the first andsecond sources and doped a second conductivity type; forming sourcerungs within the intermediate region; wherein forming the first andsecond sources, forming the body regions and forming the source rungseach comprise employing a self-aligning technique further comprisingmasking the first and second sources, masking rung regions connectingthe first and second sources and counterdoping exposed regions to asecond conductivity type; wherein a body region is disposed between twoconsecutive source rungs, each source rung extending in the X directionand the source rungs spaced-apart in the Z direction, each source rungconnecting the first and second sources at different locations along thefirst and second sources; and determining a ratio of a source rung areaand a body region area to control a contact resistance between of thesource rungs and the body regions.

In another embodiment, a semiconductor device is provided. Thesemiconductor device comprises at least a first and a secondsemiconductor cell each comprising material regions extending in a Zdirection, the regions spaced apart in an X direction; the first and thesecond semiconductor cells each comprising: a substrate; a drain contacton a first surface of the substrate; an epitaxial layer on a secondsurface of the substrate, the second surface opposite the first surface,the epitaxial layer doped a first dopant type; a first doped regionextending in a Y direction from an upper surface of the epitaxial layerand doped a second dopant type; a first and a second source spaced apartin the X direction, disposed within the first doped region, and dopedthe first dopant type, the first and second sources formed in aself-aligned manner relative to the first doped region; source rungs inthe first doped region, each source rung connecting the first and secondsources at a different location along the first and second sources, thesource rungs alternating with first doped regions and formed in aself-aligned manner relative to the first and second sources, the sourcerungs comprising dopants of the first dopant type; and wherein an areaof the source rungs and an area of the first doped regions areindependently determinable responsive to a contact resistance of thesource rung and a contact resistance of the first doped region.

DRAWINGS

FIG. 1 depicts a prior art power MOSFET.

FIGS. 2 and 3 depict respective top and cross-sectional views of a priorart power MOSFET comprising a plurality of individual cells oriented ina stripe configuration.

FIG. 4 depicts a cross-sectional view of a power MOSFET structure.

FIGS. 5-9 are perspective views illustrating formation of variousfeatures of the power MOSFET of FIG. 4 during successive process steps.

FIG. 10 depicts a coordinate system for use in describing embodimentspresented herein.

DETAILED DESCRIPTION

Before describing in detail the particular power MOSFET and the methodsfor forming such a power MOSFET (and the individual cells thatconstitute the power MOSFET) it should be observed that embodimentspresented herein include a novel and non-obvious combination of elementsand fabrication steps. So as not to obscure the disclosure with detailsthat will be readily apparent to those skilled in the art, certainconventional elements and steps have been presented with lesser detail.

The presented embodiments are not intended to define limits of thestructures, elements or methods of the inventions, but only to provideexample constructions. The embodiments are permissive rather thanmandatory and illustrative rather than exhaustive.

One advantageous feature that may be present in some embodimentsprovided herein is the channel-source self-alignment accomplished byforming strategically placed spacers for use during subsequent dopingsteps. Another advantageous feature that may be present in someembodiments provided herein is the ability to control or determine, andtherefore change, the areas of the body and source contacts (ohmiccontacts).

In one embodiment, a self-aligned NMOSFET process is provided that canbe advantageously used to shrink cell pitch and substantially reduce thelithography challenges for small, center-cell P+ contacts (i.e., thecontacts located in a center region of the P+ body region).

Generally, self-alignment of doped regions is characterized by alignmentof one layer or feature in a semiconductor device to another layer orfeature as a result of physical processes not directly related tooptical lithography. For example, in fabricating a conventional MOSFET,the gate oxide and gate contact are formed over the substrate. The oxideis etched from over the source and drain regions while the gateelectrode blocks the etchant from reaching the underlying gate oxide.After this etch step, the source and drain regions are implanted withdopants. Thus the gate oxide and gate contact align the source and draindoped regions with the gate structures by defining the location of thesource and drain regions and also serve as a doping block while thesource and drain dopants are implanted.

In some embodiments, use of spacers and spacer extensions, as describedbelow, define the regions to be doped or counter-doped. The spacer andspacer extensions are formed and their dimensions controlled by physicalprocesses, rather than photolithography techniques. Use ofself-alignment techniques allows the designer to further shrink the sizeof cell elements, packing more MOSFET cells into a MOSFET device therebyincreasing the current capacity of the device.

The benefits of self alignment generally include allowing the formationof smaller feature size elements and avoiding lithographic defects(e.g., mask misalignment, alignment tolerances, and resist errors).Self-alignment tolerances are instead controlled by physical processes.As an example, self-alignment through spacer formation, as describedbelow, is achieved by properly proportioning a spacer width relative toa thickness of a CVD deposited hard mask film. The hard mask filmthickness and the deposition process that controls it is adjustable overa useful range and easily verified through common fabrication opticalmetrology tools. Thus this process sequence results in controllablesubmicron features.

The strip cell design presented herein, which is used to scale theMOSFET size, is optimized using self-alignment techniques. This designachieves both improved yield and improved performance.

An XYZ coordinate system (see FIG. 10) is used as a reference system todescribe the various features illustrated in the figures of theapplication. An X axis is defined from a right side to a left side ofthe structure, with the X value increasing moving from left to theright. A Y axis extends vertically with Y=0 defined at a surface of aninitial semiconductor material, with positive Y values extendingdownwardly into the semiconductor substrate and negative Y valuesextending upwardly. A Z axis extends into the paper or display surface,increasing in value extending into the paper or display surface. Thethree axes system of FIG. 10 is merely exemplary and convenientlyinstructive for describing the presented embodiments. As known by thoseskilled in the art, the system can be rotated to form other coordinatesystems, for example, with the Z-axis pointing down, while satisfyingthe right hand rule that governs the relationship among the X, Y and Zaxes. While the elements of the presented embodiments are describedrelative to the coordinate system of FIG. 10, other orientations of theelements according to other coordinate systems are deemed to fall withinthe scope of the presented embodiments.

A cell pitch is defined as an X-direction distance between a feature inone cell and the same feature in an adjacent cell, where each cellcomprises features (source, body, well, etc.) that extend in the Zdirection. An XY plane comprises a plane formed by the X and Y axes ofthe coordinate system.

FIG. 4 depicts a cross-sectional view of a power MOSFET 100. Asillustrated, the MOSFET 100 comprises a drain contact 104, an N+substrate 108, an N− drift region 110 (or epitaxial layer 110), P-wells114 and 115, P+ body regions 118 and 119, and N+ source regions 122,123, 124 and 125. The drain contact 104 can be regarded as disposed on afirst surface of the N+ substrate 108 and the epitaxial layer 110disposed on a second surface of the N+ substrate 108. The various dopedand undoped layers or regions of the MOSFET device may also be referredto as material layers or material regions.

As illustrated, the P+ body regions 118 and 119 are disposedapproximately in a central region of the respective P-wells 114 and 115.The P-wells 114 and 115 have a generally U-shape comprising anintermediate region (the P+ body regions 118 and 119 disposed in therespective intermediate regions) between two upright legs. The N+ sourceregions 122, 123, 124 and 125 are spaced apart from respective end walls114A, 114B, 115A and 115B of the P-wells 114 and 115.

Gate contacts 130 (typically comprising polysilicon) and a gate oxidelayer 134 overlie portions of the N+ source regions 122, 123, 124 and125 as illustrated, and end regions of the P-wells 114 and 115 asillustrated. Source contact stripes 128 (typically comprising aluminumoverlying a contact metal, e.g., nickel) are disposed in contact withthe P+ body regions 118 and 119 as shown in FIG. 4. The source contactstripes 128 also contact the source regions 122, 123, 124 and 125outside the plane of FIG. 4 and are discussed in conjunction with FIG.9.

Inter-layer dielectric (ILD) layer 139 electrically isolates the sourcecontact stripes 128 from the gate contact 130 to prevent gate-to-sourceshorts. A source contact metal layer 140 (in one embodiment about 4 μmthick) is formed over the ILD layer 139 and the source contact stripes128.

Channel regions 142 are formed within the P-wells 114 by application ofa positive voltage on the gate contact 130 that exceeds a gate thresholdvoltage of the MOSFET. When the channel is formed, current can flow fromsource to drain as in any conventional MOSFET.

The following figures depict process flow steps and the resulting formedstructures along a small portion of a MOSFET stripe.

The features illustrated in FIGS. 5-9 can be reflected along a rightside surface 200 of FIG. 5 and along a left side surface 201 to form aplurality of stripes (in the X direction) in the final power MOSFET.Also, the various described regions (e.g., source, body, well) extend inthe Z direction.

A line 150 in FIG. 4 indicates regions of the FIG. 4 cross-section thatare illustrated in FIGS. 5-9.

FIG. 5 illustrates a drain contact 214 (referred to as a backside draincontact) disposed on one surface of an N+ substrate 216. The draincontact 214 is conventionally formed during the final fabrication stepsfor forming the MOSFET. An N− epitaxial drift layer 220 is formedaccording to known techniques over the N+ substrate 216.

First and second parallel spaced-apart hard masks 224 and 225, eachhaving a respective vertical sidewall 224A and 225A, are formedaccording to known techniques (e.g., blanket depositing a first blankethard mask followed by hard mask etching) over a respective region of anupper surface of the epitaxial drift layer 220. Generally, a center lineextends in a Z direction between the hard masks 224 and 225.

A P-well region 228 is formed in an upper region of the N− epitaxiallayer 220 and between the hard masks 224 and 225 (i.e., the hard masks224 and 225 masking or covering the structures below the hard masks 224and 225) by implanting a P type dopant (counterdoping) to counter-dopethe N− epitaxial layer 220. Typically the P-well extends in a Ydirection about 1 μm or less from an upper surface 228A of the P-wellregion 228. Other P-well depths may be attained with higher energy ionimplantations, noting that there is little vertical ion or dopantdiffusion in silicon carbide. As shown, the P-well region 228 extends inthe Z direction.

The hard masks 224 and 225 extend over the entire upper surface of theN− epitaxial drift layer 220 before the etching process is performed.FIG. 5 actually illustrates a cut-away view as upper surfaces of theP-well 228 and the N− epitaxial drift layer 220 are both visible in theFigure.

A chemical vapor deposition (CVD) process forms a second blanket hardmask over the structure, followed by a directional etch to form firstand second hard mask spacers 232 in FIG. 5. The spacers 232 areself-aligned to the P-well region 228 and overlie edge regions of theP-well region 228, shielding the regions that they overlie during asubsequent dopant implantation step. In effect, a centerline of the cellpasses between the first and second spacers 232. The dimensions of thespacers 232 are precisely controlled by controlling a depositionthickness of the hardmask material and by controlling the directionaletching process. Precise dimensional control of the dimensions of thespacers 232 fixes the controllable and uniform submicron channellengths, as the channels will be formed during MOSFET operation in thoseregions of the P-wells 228 that are immediately below the spacers 232.

Implanting N+ ions into exposed regions of the P-well region 228 formsan N+ region 234 (from which the source regions will later be formed)within an upper surface of the P-well region 228 (i.e., a counterdopingprocess). The N+ implant doses are higher than the doping of the P-wellregion, thus compensating the P-well region doping to create the N+region 234. During the implant process the hard masks 224, 225, and 232prevent implanting ions in regions below these hard masks. This step ofimplanting source ions allows for self-alignment of the channel to thelater-formed sources.

A third blanket hard mask 240 (see FIG. 6) is formed as a blanket layerthat completely covers an upper surface of the structure (only a portionof the third hard mask 240 is illustrated in FIG. 6). A resist stripe244 is formed atop the hard mask 240 across a complete width of thestructure. Multiple such resist stripes are formed each extending in theX-direction and the multiple resist stripes spaced-apart along theZ-direction.

The hard mask 240 is directionally etched (with a predominant verticalcomponent) to remove all regions of the hard mask 240 except the regionsbeneath the resist stripe 244 and except first and second spacerextensions as described below. After the hard mask etch, the resist isremoved to leave a hard mask region 240A as shown in FIG. 7.

The directional etch also forms first and second spacer extensions 250(adjacent the first and second spacers 232 such that the cell centerlinealso extends between the first and second spacer extensions 250) thatserve as masks to provide self-alignment for a subsequent compensating(counterdoping) P+ implant into the N+ region 234 that forms a bodyregion, such as the body region 119 of FIG. 4. The spacer extensions 250extend toward a center line of the cell in the range of about 0.25 toabout 2.0 μm measured from an edge of the spacers 232.

FIG. 8 illustrates a P+ body region 252 formed by counterdoping the N+region 234 with the hard mask region 240A (shown in FIG. 7) in place andshielding regions of the N+ region 234 from the implant ions. Theshielded regions will become the sources as described below.

After removing the hard mask region 240A, the device (referred to as aunit cell of the power MOSFET) resembles FIG. 8. The cell doping iscomplete. As illustrated in FIG. 8, the unit cell comprises the P-well228 and first and second N+ sources 260 (or source region stripes 260)extending along the cell length (i.e., in the Z-direction). Althoughonly two P+ body regions 252 and one N+ source rung 262 is shown in FIG.8, the complete cell comprises a plurality of P+ body regions 252alternating with the N+ source ladder rungs (or source rungs) 262 alongthe cell length. The source rungs 262 connect the first and second N+sources 260 at different locations along the first and second sources260.

All these MOSFET features have been formed using the describedself-alignment processes. In particular, the N+ source regions ladderrungs 262 are self-aligned to the channel (which is formed within theP-well 228 during operation of the device) and the edges of the P+ bodyregion 252 are self-aligned to the N+ source region stripes 260.

A cell pitch dimension is identified by a reference character 270 and aunit cell length dimension by a reference character 274 in FIG. 8.

It can be seen from comparing FIGS. 4 and 8 that the two source regions122 and 123 in FIG. 4 comprise the two parallel source regions stripes260 in FIG. 8. The P+ body region 118 comprises the P+ body region 252in FIG. 8. The P-well 114 comprises the P-well 228 in FIG. 8. The line150 in FIG. 4 indicates the regions of the FIG. 4 cross-section that areillustrated in FIG. 8. The source regions 124 and 125, the P+ bodyregion 119 and the P-well 115 on the right side of FIG. 4 representanother contact stripe that is not shown in FIG. 8.

After the processes associated with FIG. 8 have been completed, the cellis annealed to activate the implanted ions. Any exposed oxide on thewafer will not survive at the anneal temperature; the wafer is thereforestripped bare and coated with a high temperature overcoat material toprevent the silicon atoms from diffusing out from the wafer into the gasphase during the anneal process. Alternatively, the anneal process isperformed using silane as the ambient gas. The silane gas partialpressure prevents the evaporation of the silicon atoms from the wafercell.

FIG. 9 illustrates a single continuous contact 290 (or a contact stripe290) that is also formed after the anneal step. The contact 290 contactsboth the P+ body regions 252 and the N+ source rungs 262, which are inconductive communication with the source region stripes 260.

The structures above the upper surface of the cell (as depicted in FIG.4) are then formed. The gate oxide (reference character 134 in FIG. 4)is grown and patterned and the gate polysilicon contact (referencecharacter 130 in FIG. 4) is formed. The inter-layer dielectric(reference character 139 in FIG. 4) is deposited and a contact windowstripe is opened in the ILD to permit contact to the continuous contactstripe 290. This effectively permits contact to the P+ body regions 252,the N+ source region ladder rungs 262 and the source regions stripes260, which are all in electrical communication with the contact stripe290.

Note that contact with both the P+ body regions and the source regionladder rungs are made along a single stripe, thereby avoiding the tighttolerances required by lateral P+ and N+ regions of a conventionalMOSFET. This feature permits smaller stripe pitch with an increase inchannel density, which reduces the R_(DS(ON)) parameter. Theself-alignment processes and ladder cell geometry presented hereinreduce the design and manufacturing constraints that are placed on theohmic contact pattern, since the contact pattern is formed by the singlestripe across both N+ source rungs and P+ body regions. Use of thesingle stripe allows the lateral cell width dimensions to be minimized.

Note also in FIG. 9 that the P-well region 228 and the P+ body region252 are in contact, essentially creating a continuous P type region.This feature can also be seen in FIG. 4 relative to the P-well regions114 and 115 in contact with respective P+ body regions 118 and 119. Thusthe ohmic contact between the contact stripe 290 and the P+ body region252 fixes the potential at both the P+ body region 252 and the P-wellregion 228.

Note that the ohmic contact to the N+ source region ladder rungs alsoserves as the ohmic contact to the N+ source region stripes 260, sincethe rungs and the stripes are in contact.

The depth of the P+ body region 118 or 119 in FIG. 4 is illustrated asdeeper than the N+ source regions 122, 123, 124 or 125. Whereas in FIG.9, the P+ body region 252 is shown at approximately the same depth asthe source regions stripes 260. Since dopants undergo very littlediffusion in silicon carbide, the dopant depths are determinedsubstantially by the dopant implant energy. Controlling that implantenergy thus determines the dopant depth profiles. The implant energy,and as a consequence the dopant depths, is selected based on the desiredoperating parameters of the final MOSFET. Thus the dopant profilesillustrated in FIGS. 4 and 9 may be appropriate.

It is known that when aluminum is used as the contact metal for siliconMOSFETS (or for any silicon-based semiconductor), a good low-ohmiccontact can be formed for both P type and N type regions. But, this isnot the case with silicon carbide.

Nickel is typically used for contacts to N-doped SiC materials with goodresults, i.e., a low resistance ohmic contact. But using nickel as thecontact metal for P-doped regions does not yield a low contactresistance. To overcome this disadvantage an area of each contact regioncan be determined to minimize the contact resistance of the P+ bodyregion when nickel is used as the contact metal.

Use of the ladder cell configuration (and the corresponding fabricationmethodology) may allow the use of geometric compensation to overcome theadverse effects of the high contact resistance associated with the usenickel contacts to P-type doped regions. That is, the area of the N+source region ladder rungs 262 and the area of the P+ body 252 can bevaried (within a given cell unit length) to yield two relatively lowcontact resistances. Varying the individual areas can also vary theratio of the areas; thus this technique is also referred to as arearatio control. The areas are varied by altering the area of the hardmask and resist stripe that are used to form these structures.

The benefits of the ladder cell geometry are evident particularly whencombined with the self-aligned described contact process. For example,employing the designs and processes presented herein, it may be possibleto reduce the cell pitch from about 11.0 μm to about 8.8 μm, a reductionof 20%.

As can now be appreciated, the teachings presented herein can beemployed to fabricate MOSFET cells as densely as desired up to a maximumchannel length per unit area. Also, self-alignment of the various dopedregions by using hard masks and hard mask extensions forms source regionladder rungs across the cell. Further use of an ohmic contact stripeavoids alignment issues that require tight tolerances. This tightens theside to side tolerances of cell while at same time shrinking side toside dimensions (thereby yielding more channels per unit area).

Electrical contact along the source region ladder rungs 262 does notrequire a close alignment tolerance when the ILD 139 (see FIG. 4) isopened to access the rungs. Due to certain lithography constraints, itis generally easier to maintain a tight tolerance for a line featurethan for a closed area feature. Embodiments presented herein takeadvantage of that premise to access a contact on the ladder rungs 262.This ability to maintain tight line tolerances allows reducing the cellpitch and placing more stripes within the MOSFET device or more channelsper device area.

Although the embodiments presented herein have been described in thecontext of a silicon carbide semiconductor device, those skilled in theart recognize that the described methods and structures can be employedwith silicon or silicon carbide semiconductor materials, and with anysemiconductor material that can be doped to form P and N regions and PNjunctions where those regions are in contact.

In another embodiment an area ratio of the area of the N+ source regionladder rungs 262 and the area of the P+ body 252 is graded (i.e. variedas a function of location or distance from a predetermined point orline). This technique increases the efficiency of one contact atdifferent locations on the device. For example, regions that are fartherfrom the gate contact are less efficient than those closer to the gatecontact. An increase in efficiency and reliability may result if thecontact resistance is relatively higher at regions that are closer tothe gate contact and lower at regions that are more distant from thegate contact.

The various elements of the MOSFET device have been described as stripedelements. See for example, the P-well region 228 and the N sourceregions stripes 260. However, in another embodiment the device elementsmay be formed in a rectangular shape if the aspect ratio of therectangular shape is sufficiently large to accommodate a sufficientnumber of N+ source region ladder rungs 262 each of sufficient length.

In one embodiment a Z-direction length of the P+ body region 252 isabout 6 μm and the N+ ladder rungs 262 can be as short as 2 μm. A repeatinterval in the Z direction for the cells that comprises a MOSFET isabout 8 μm (6+2=8 μm). A cell pitch can range from a minimum value ofabout 7.0 μm.

A MOSFET device fabricated according to processes presented herein mayhave an on state specific channel resistance of as low as about 1milliohms-cm̂2 and a lower limit for the specific drain-source resistanceof about 5 milliohms-cm̂2. To determine these specific resistance values,certain assumptions were made regarding physical parameters, dimensions,process technologies, and voltages (e.g., threshold voltage andbreakdown voltage) for the MOSFET under consideration. Changing one ormore of these underlying assumptions will alter the specific channel andspecific drain-source resistance values from those given.

The various described embodiments may display all the advantages of theprior art vertical MOSFETS, but importantly may allow contact areaadjustment (area ratio control) to overcome the disadvantages associatedwith the contact resistance to a P-type SiC semiconductor material.

While various embodiments have been described, many variations andmodifications will become apparent to those skilled in the art.Accordingly, it is intended that the inventions not be limited to thespecific illustrative embodiments but be interpreted within the fullspirit and scope of the appended claims.

Although described primarily with reference to use in power MOSFETS, thetechniques and structures presented herein can also be employed withother vertical MOSFETS or in other semiconductor devices.

Although described for an NMOSFET, the teachings are also applicable toa PMOSFET and the processing steps for forming a PMOSFET.

This written description of the embodiments of the invention usesexamples to disclose the inventions, including the best mode, and alsoto enable any person skilled in the art to make and use the inventions.The patentable scope of the inventions is defined by the claims, and mayinclude other examples that occur to those skilled in the art. Suchother examples are intended to be within the scope of the claims if theyhave structural elements or process steps that do not differ from theliteral language of the claims, or if they include equivalent structuralelements or process steps with insubstantial differences from theliteral language of the claims.

1. A semiconductor device comprising: at least a first and a secondsemiconductor cell each comprising material regions extending in a Zdirection, the regions spaced apart in an X direction; the first and thesecond semiconductor cells each comprising: a substrate; a drain contacton a first surface of the substrate; an epitaxial layer on a secondsurface of the substrate, the second surface opposite the first surface,the epitaxial layer doped a first dopant type; a first doped regionextending in a Y direction from an upper surface of the epitaxial layerand doped a second dopant type; a first and a second source spaced apartin the X direction, disposed within the first doped region, and dopedthe first dopant type, the first and second sources formed in aself-aligned manner relative to the first doped region; source rungs inthe first doped region, each source rung connecting the first and secondsources at a different location along the first and second sources, thesource rungs alternating with first doped regions and formed in aself-aligned manner relative to the first and second sources, the sourcerungs comprising dopants of the first dopant type; and wherein an areaof the source rungs and an area of the first doped regions areindependently determinable responsive to a contact resistance of thesource rung and a contact resistance of the first doped region.
 2. Thesemiconductor device of claim 1, wherein the first doped regioncomprises: a well extending between the first and second sources in thefirst semiconductor cell, the well doped the second dopant type; a bodywithin a central region of the well, and doped the second dopant type;the well and the body formed using a third mask to self-align the wellrelative to the body; and wherein during operation of the semiconductordevice a channel is formed in an end region of the well of the firstsemiconductor cell and in a proximate end region of the well of thesecond semiconductor cell.
 3. The semiconductor device of claim 2,wherein a dopant concentration of the body is greater than a dopantconcentration of the well and wherein a depth of the body is less than adepth of the well.
 4. The semiconductor device of claim 1, wherein thefirst and the second dopant types comprise respectively N type dopantsand P type dopants or respectively P type dopants and N type dopants. 5.The semiconductor device of claim 1, wherein a material of the sourcecontact comprises nickel.
 6. The semiconductor device of claim 1,wherein a ratio of the area of the source rungs and the area of thefirst doped regions is determinable responsive to a contact resistanceof the source rung and the contact resistance of the first dopedregions.
 7. The semiconductor device of claim 1, wherein the ratio isgradeable by varying one or both of the area of the source rungs and thearea of the first doped regions.
 8. The semiconductor device of claim 1,wherein the first doped region and the first and second sources compriseone of a stripe shape and a rectangular shape.
 9. The semiconductordevice of claim 1, wherein the semiconductor device comprises a MOSFETdevice having an on-state specific channel resistance of about 1milliohms-cm̂2.